Synchronising cell transmission for packet switching

ABSTRACT

The invention relates to a method and a packet switch for synchronising port controllers ( 1 ) with cross-connection means ( 40 ). By switching cross-connection means from loopback configurations ( 41   a,    43   a ) to no-transmission configurations, consecutively an offset counter ( 32 ) in a port controller ( 1 ) may be altered until transmission of cells is synchronised, so as cells are switched within said cross-connection means ( 40 ) within transmission periods.

The invention relates to a method for synchronising start of cell timesin input/output means with cell transmission periods in at least onecross-connection means for packet switching, where cells are transferredbetween said input/output means by said cross-connection means in celltransfer periods, where configurations of said cross-connection meansare changed between cell transfer periods in cross-connectionconfiguration periods, where cells from said input/output means are sentat start of cell times, and where said sent cells are received in saidcross-connection means. The invention further relates to a packet switchcomprising input/output means, with a port controller, with a cell inputport, and a cell output port, cross-connection means comprising cellinput ports and cell output ports connected to said cell output port andcell input port of said port controllers, respectively. Furthermore, theinvention relates to the use of such a method and such a packet switch.

Switching-nodes of packet switched networks comprise packet-switches.These packet-switches transfer data packets between input and outputports, based on address information comprised in each incoming packet.Incoming packets are buffered in line cards and organised in input portqueues. These input port queues are organised as virtual output queues(VOQ), which are implemented inside a port controller, located on a linecard. These port controllers are connected to switch cards, comprisingcrossbar matrices and an arbiter, respectively, by cables. The arbitercalculates input/output configurations of the matrices to allow an eventransmission of incoming packets of all connected port controllers. Toswitch the incoming packets to the respective output ports, the crossbarmatrices connect input ports with the respective output ports duringcell transfer periods. To change the connections between input andoutput ports, the configuration of the matrices have to be changed bythe arbiter during switch-over times.

Incoming packets are segmented within the line cards into fixed sizepacket fragments, also called cells. Outgoing packets are reassembledfrom cells which have been switched from a crossbar matrix to therespective line card.

To allow a smooth transmission of incoming packets, the arbiter works inclose co-operation with the port controllers on the line cards. Eachport controller sends a regular update of its VOQ state to the arbiter.The arbiter keeps a copy of the actual state-information of the VOQs ofall connected port controllers. Based on the VOQ state-informationreceived from the connected port controllers, the arbiter calculates theI/O configuration of the matrices and sends the result to the matrices,respectively, and the port controllers at regular intervals.

In FIG. 1, a known system is depicted. A plurality of line cards 1-N isconnected to a number of switch cards 10. The line cards 1-N communicatewith the switch cards 10 by using port controllers 1 a-Na. The portcontrollers 1 a-Na send data cells to and receive data cells from theswitch cards 10 via connection lines 2, 4. The state information of theoutput queues of the port controllers 1 a-Na are communicated toarbiters 10 b via communication lines 6, 8. The arbiters 10 b decidewhich line cards 1-N are connected with each other via the lines 4, 2 totransmit respective cells in the output queues of the port controllers 1a-Na.

The transmission of cells between port controllers 1 a-Na is switched bysetting a crossbar matrix 10 a appropriately. Input ports of the switchcards 10 are represented by lines in the crossbar matrix 10 a. Outputport of the switch cards 10 a represented by columns in the crossbarmatrix 10 a. To connect, for example, input port “1” with output port“3”, a switch located at line 1 at column 3 of a matrix 10 a is set“on”.

In case the crossbar matrix 10 a, or the switch 10 does not comprise abuffer memory, instant switching has to be provided, otherwise incomingpackets would be corrupted when switching between a first configurationto a second configuration of crossbar matrix 10 a is carried out duringtransmission of said cell.

A crucial function for a buffered matrix to work properly is thealignment of incoming cells. Only if incoming cells are aligned,configurations of the matrix can be changed without disturbing celltransfers. An exact alignment is best for synchronisation.Synchronisation of the cells at the input of the crossbar matrix iscomplicated, because the cables connecting port controller 1 a-Na withcrossbar matrix 10 a may be of different lengths. Different lengthscause different signal time delay on the lines. With data rates ofseveral Gbit/s, a difference of some centimetres of the line lengthresults in a misalignment of the cells for a couple of bit clocks.

From JP 7-79218 it is known to provide a synchronisation patterndetection circuit. The synchronisation pattern detection circuit detectsframes and synchronisation patterns from information stored in a shiftregister. By transmitting a sync signal, a fixed difference oftransmission times is calculated and a synchronisation pattern isevaluated. By applying the synchronisation pattern, wire length can bedifferent, as the input is synchronised by using the synchronisationpattern. A problem of generating synchronising patterns is that eachline card must generate such a synchronisation pattern and each switchcard must derive the synchronisation pattern from the line card.

Thus, it is an object of the invention to provide a method and a systemthat allows independent alignment of cells by the line cards. A furtherobject of the invention is to provide a flexible system configuration,being able to allow synchronisation in different configurations. Afurther object of the invention is to provide packet switching withoutbuffer memory in the crossbar matrices.

The objects of the invention are solved by oscillating saidconfiguration during a set-up period between a loopback configurationand a no-transmission configuration, whereby received cells aretransferred back to said sending input/output means in said loopbackconfiguration and received cells are not transferred back to saidsending input/output means in said no-transmission configuration,receiving back transferred cells in said input/output means, checkingsaid received cells in said input/output means for a transmission error,and shifting an offset of said start of cell times in case atransmission error occurred, until transferring back at least one cellis wholly carried out within a cell transfer period.

The configuration of the cross-connection means is changed betweenloopback configuration and no-transmission configuration. In loopbackconfiguration, incoming cells are transferred back to the sendinginput/output means, for instance a port controller. In no-transmissionconfiguration, incoming cells are not sent back to the sendinginput/output means.

In case cells are transferred back, these cells are received in saidinput/output means. As the configuration of the cross-connection meansis switched between loopback configuration and no-transmissionconfiguration, transmitted cells may be corrupted. Corruption of cellsmay appear, if they are received in the cross-connection means duringtimes of configuration, e.g. cross-connection configuration periods,also called switch-over periods. Corruption may also occur, if parts ofthe cells are received during transmission periods and parts of thecells are received during no-transmission periods. Only in case the cellis received and re-transmitted wholly within a transmission, or loopbackperiod, it is received without transmission error.

By shifting the offset of start of cell times, the input/output meanstries to find the correct time, at which cells may be transmitted andfurther processed within the cross-connection means without falling intoa switch-over period or a no-transmission period. The offset is shifteduntil at least one cell is wholly re-transferred within a cell transferperiod. In that case an input/output means has determined the times atwhich it may send cells, so that they are not corrupted due to matrixconfigurations.

Port controllers and separate line cards, being connected to thecrossbar matrix by cables of different lengths may be aligned so thattheir cells are received within the matrix at equal times. The loopbackconfiguration is active for one cell transfer period and theno-transmission configuration is also active during one celltransmission period. In no-transmission configuration, ongoing celltransfers are disturbed. Only if the offset is such that the whole cellis transmitted within loopback configuration, the input/output means aresynchronised with the cross-connection means.

An alignment of all incoming cells from connected input/output means ismade available according to claim 2. In this case the transmission datarate may be at its maximum, as transmission periods only last forexactly one transmission of a cell.

A central clock signal, according to claim 3, allows easy cellsynchronisation.

Serialisation and de-serialisation, according to claim 4 and 5, allowsserialised transmission of data packets. Evaluating a bit errorindicator, according to claim 6, may also be carried out based on acoding scheme applied for transmission on a transmission line. Theoutput of the bit error indication may be used as decision to change theoffset of start of cell times in order to delay the output of cells.

Using an offset counter, according to claim 7, allows a shift of thestart of cell times of outgoing cells with respect to a matrixconfiguration synchronisation signal. The delay is incremented ordecremented by defined step widths.

The offset counter may also be controlled, according to claim 8, in away that the start of cell time is pre-running with respect to the startof cell signal as much as possible without generation of bit errors, andafterwards delaying the start of cell time as much as possible until biterrors occur. The length of cell transmission periods may then beadjusted and the total throughput is increased. The bit error rate isbrought to a minimum in case the start of cell time is set according toclaim 9.

According to a further aspect of the invention, a packet switch isprovided, where said port controller comprises a start of cell signalgenerator for generating start of cell signals, an offset controller forshifting a start of cell time based on said start of cell signal, and anerror detection mean for detecting corrupt received cells and where saidcross-connection means comprises a configuration controller forcontrolling an oscillation between a loopback configuration and ano-transmission configuration of said cross-connection means.

A packet switch, according to claim 11, is advantageous, as a centralclock signal allows exact synchronisation between port controllers andcross-connection means.

By providing serialisation and de-serialisation means, according toclaim 12, data bits or packets may be serially transferred.

Providing an N×N cross matrix, according to claims 13 and 14,configuration changes may be applied easily. In such a matrix, a linecorresponds to an input port and a column corresponds to an output port.A switch at position (X, Y) in said N×N matrix connects input port Xwith output port Y.

By providing a bit error indicator, according to claim 15, a bit errormay be derived from the coding scheme applied for a transmission on aline.

Another aspect of the invention is the use of a described method or adescribed packet switch in packet switched networks for synchronisingstart of cell times in various port controllers during a set-up, toallow configuration changes in cross-connection means without disturbingcell transfers.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter.

In the figures show:

FIG. 1 a packet switch configuration;

FIG. 2 diagrammatically the variation of the offset of start of celltimes;

FIG. 3 a block diagram of an inventive packet switch.

FIG. 2 depicts in diagrams A-E a succession of cells being send within aset-up period of a packet switch.

As can be seen in diagram A, data cells 12 are usually sent at start ofcell times 14, which usually correspond to a start of cell signal 16.Usually, a data cell 12 is sent exactly after a start of cell signal 16is generated. In that case, all cells from all port controllers are sentat the same time. As cables connecting the port controllers with thecrossbar matrices may have different length, the cells are received inthe matrices at different times. For switching packet switchedconnections, the configuration of the matrices have to be changed.During these configuration periods 20, cells 12 may be received withinthe matrices, which causes cell corruption. The invention provides amethod to set up a packet switch in a way, that cell corruption may beavoided.

The configuration of a crossbar matrix of a switch card is changed, asdepicted in diagram B, between configuration B₁ and configuration B₀during a set-up period. Configuration B₁ stands for loopbackconfiguration, where the matrix is a unit matrix, and configuration B₀stands for no-transmission configuration, where the matrix is a nullmatrix.

During a set-up period of the crossbar matrix, the configuration ischanged between B₁, and B₀. In configuration B₁, cells 12 sent from aport controller 1 a are sent back to this respective port controller 1a. During no-transmission time B₀, cells 12 sent from port controller 1a are not sent back to port controller 1 a. The inventive method worksas follows.

As depicted in diagram C, start of cell signals 16 are generated in allport controllers according to a common clock signal at system start.Cells 12 are sent at start of cell times 14 and received in the crossbarmatrix during loopback configuration B₁, no-transmission configurationB₀, and set-up period 20.

First, cells are released from the cell memory at start of cell times 14directly after reception of the start of cell signal 16. An offset maybe generated, by which the start of cell time 14 is shifted from thestart of cell signal 16 by a certain value. In case sent cells 12 arereceived in the matrix during set-up period 20 or no-transmissionconfiguration B₀, they are not correctly sent back to the sending portcontroller. The received cells are corrupt. To recognise corrupt cells,each received cell is evaluated and thus transmission errors aredetected. In case a transmission error is detected, the cell 12 has beenreceived in the matrix at times where the transmission becomes corrupt,e.g. no-transmission period B₀ or set-up period 20.

The offset is increased incrementally, the start of cell time 14 isincrementally delayed from the start of cell signal 16, until the cell12 will be sent at a time where it can be received in the matrix withinthe loopback configuration time B₀ and thus sent back to the portcontroller without error. The offset will then not be increased further,and may be used during the operation of port controller, as it allows anerror-free transmission of cells.

In diagram D, the offset of the start of cell time 14 is decreased.First, a cell is sent at times at which it is received in the matrixduring set up period 20. In that case a cell 12 is corrupted. Byshifting the offset, the start of cell time 14 is pre-running the startof cell signal to a further extend. After a few shifts, the start ofcell time 14 will be such, that a cell 12 will be wholly received withinsaid crossbar matrix during period B₁.

According to diagram E, the offset is controlled in a way that the startof cell time 14 is at first pre-running with respect to the start ofcell signal 16 as much as possible without generating bit errors, andafterwards decreased as much as possible until bit errors startappearing. By this, the duration of a loopback configuration B₁ isevaluated and the start of cell time 14 can be adjusted such that a cell12 will be transmitted in the middle of transmission time. Also the gap13 between cells 12 may thus be decreased to a minimum value.

FIG. 3 depicts a port controller 1 and a crossbar matrix 40. Portcontroller 1 provides an input port 24, an output port 26, a cell memory28, a start of cell signal generator 30, an offset counter 32, aserialiser 34, a de-serialiser 36 and a bit error indicator 38. Crossbarmatrix 40 provides cell input ports 41, cell output port 43, switchedconnections 42 and interrupted connected 44. Further depicted is acentral clock generator 48 and a configuration controller 46.

Incoming packets at port 24 are segmented into fixed sizes packetfragments, cells, and stored in cell memory 28. Outgoing cells arereassembled back into packets and put out at port 26. During set-up of aport controller 1, cells are sent at start of cell times which aregenerated at the start of cell time generator. These packets areserialised in serialiser 34 and sent to cell input port 41 a. Inloopback configuration, cell input port 41 a is switched to cell outputport 43 a.

Loopback configuration means that a unit matrix of the switches 42, 44is generated, whereby an input port 41 a, b is switched to an outputport 43 a, b, respectively. The unit matrix means that each input portis switched to its respective output port and no other connection isswitched. These ports being switched belong to one same port controller.The switches 42 are “on” the switches 44 are “off”. This is theso-called loopback configuration.

No-transmission configuration is realised by a null matrix, where noconnections between input ports and output ports are switched at all.All incoming data-packets are lost or corrupted. All switches 42, 44 are“off”.

During set-up the crossbar matrix 40 is switched between unit matrix andnull matrix by configuration controller 46, which is controlled by asystem clock signal generated by central clock generator 48. The systemclock generated by central clock generator 48 is also provided to offsetcounter 32 and to start of cell signal generator 30. Cells which areretransmitted to port controller 1 are received in the serialiser 36.The received cells are evaluated in bit error rate indicator 38. In casea bit error occurred, the offset counter 32 is increased. By increasingthe offset counter 32 the start of cell signal generator generates astart of cell time prevailing the central clock signal by the amount ofthe offset counter 32. By increasing the offset counter 32, the start ofcell time will be changed until a cell is transmitted to crossbar matrix40 and received by de-serialiser 36 without transmission errors, whichmeans that the cell is received in crossbar matrix 40 in a transmissionperiod.

By applying the offset counter and the bit error indicator 38, start ofcell times may be synchronised so as to align incoming cells at matrix40 from various port controllers 1.

No central synchronisation mechanism or line length measurement isneeded, rather all port controllers adjust the cell alignmentautonomously.

Reference Signs

1, N line card

1 a, Na port controller

2, 4 transmission connection

6, 8 signalling connection

10 switch card

10 a crossbar matrix

10 b arbiter

12 cell

13 transmission gap

14 start of cell time

16 start of cell signal

B₁ loopback configuration

B₀ no-transmission configuration

20 set-up period

24 input

26 output

28 cell memory

30 start of cell signal generator

32 offset counter

34 serialiser

36 de-serialiser

38 bit error indicator

40 crossbar matrix

41 cell input port

42 switched connection

43 cell output port

44 interrupted connection

46 configuration controller

48 central clock generator

1. A method for synchronising start of cell times in input/output meanswith cell transmission periods in at least one cross-connection meansfor packet switching, where cells are transferred between saidinput/output means by said cross-connection means in cell transferperiods, where configurations of said cross-connection means are changedbetween cell transfer periods in cross-connection configuration periods,where cells from said input/output means are sent at start of celltimes, and where said sent cells are received in said cross-connectionmeans, characterized by oscillating said configuration between aloopback configuration and a no-transmission configuration during a setup period, whereby received cells are transferred back to said sendinginput/output means in said loopback configuration and received cells arenot transferred back to said sending input/output means in saidno-transmission configuration, receiving back transferred cells in saidinput/output means, checking said received cells in said input/outputmeans for a transmission error, shifting an offset of said start celltimes in case a transmission error occurred, until transferring back atleast one cell is wholly carried out within a cell transfer period.
 2. Amethod according to claim 1, characterized by shifting said offset ofstart of cell times in said input/output means, respectively, to alignthe time sent cells from said input/output means are received in saidcross-connection means.
 3. A method according to claim 1, characterizedby controlling said start of cell times, said offset of start of celltimes and said cross-connection configuration times by a central clocksignal.
 4. A method according to claim 1, characterized by calculatingstart of cell times based on a start of cell signal and said offset ofsaid start of cell times, serialising said cells, and sending saidserialised cells together with said start of cell signal at said startof cell times.
 5. A method according to claim 1, characterized byreceiving transferred back cells, de-serialising said cells and checkingeach second cell for transmission errors.
 6. A method according to claim1, characterized by receiving transferred back cells, de-serialisingsaid cells and evaluating a bit error indicator.
 7. A method accordingto claim 3, characterized by shifting said offset of start of cell timesusing an offset counter and changing said offset counter by an amount ofclock cycles of said central clock signal.
 8. A method according toclaim 1, characterized by shifting said offset of said start of celltimes to a maximum without generating transmission errors, and shiftingsaid offset of said start of cell times to a minimum without generatingtransmission errors.
 9. A method according to claim 6, characterized bysetting said offset of said start of cell times in between said maximumand said minimum.
 10. A packet switch comprising: input/output meanswith a port controller with a cell input port and a cell output port,cross-connection means comprising cell input ports and cell output portsconnected to said cell output port and cell input port of said portcontrollers, respectively, characterized in that said port controllercomprises: a start of cell signal generator for generating start of cellsignals, an offset controller for shifting a start of cell time based onsaid start of cell signal, and an error detection means for detectingcorrupt received cells, and that said cross-connection means comprises:a configuration controller for controlling an oscillation between aloopback configuration and a no-transmission configuration of saidcross-connection means.
 11. A packet switch according to claim 10,characterized in that a central clock generator is provided forproviding a central clock signal, and that said start of cell signalgenerator, said offset controller, and said configuration controllercomprise an input port for said central clock signal.
 12. A packetswitch according to claim 10, characterized in that said port controllercomprises a serialiser and a de-serialiser for serialising cells to besent and de-serialising received cells.
 13. A packet switch according toclaim 10, characterized in that said cross-connection means comprise aN×N crossbar matrix, selectively connecting N cell input ports with Ncell output ports.
 14. A packet switch according to claim 13,characterized in that said loopback configuration is realised by a unitmatrix and a no-transmission configuration is realised by a null matrix.15. A packet switch according to claim 10, characterized in that saiderror detection means is a bit error indicator.
 16. Use of a methodaccording to claim 1 or a packet switch according to claim 10 in packetswitched networks for synchronising start of cell times in various portcontrollers during a set up to allow configuration changes incross-connection means without disturbing cell transfers.